1. Field of the Invention The present invention relates to plasma displays and methods for driving the plasma displays.
2. Description of the Related Art
FIG. 1 illustrates a basic configuration of a plasma display device. A control circuit portion 101 controls an address driver 102, a common electrode (X electrode) sustain circuit 103, a scan electrode (Y electrode) sustain circuit 104, and a scan driver 105.
The address driver 102 supplies a predetermined voltage to address electrodes A1, A2, A3, . . . . Hereinafter, one or each of the address electrodes A1, A2, A3, . . . will be generally termed an address electrode Aj, where “j” is a suffix.
The scan driver 105 supplies a predetermined voltage to scan electrodes Y1, Y2, Y3, . . . in accordance with the control of the control circuit portion 101 and the scan electrode sustain circuit 104. Hereinafter, one or each of the scan electrodes Y1, Y2, Y3, . . . will be generally termed a scan electrode Yi, where “i” is a suffix.
The common electrode sustain circuit 103 supplies the same voltage to each of the common electrodes X1, X2, X3, . . . . Hereinafter, one or each of the common electrodes X1, X2, X3, . . . will be generally termed a common electrode Xi, where “i” is a suffix. The common electrodes Xi are connected to each other and at the same voltage level.
In a display area 106, the scan electrodes Yi and the common electrodes Xi form rows that extend horizontally, and the address electrodes Aj form columns that extend vertically. The scan electrodes Yi and the common electrodes Xi are alternately disposed in a vertical direction.
The scan electrodes Yi and the address electrodes Aj forms a two-dimensional matrix with i rows and j columns. The intersection of a scan electrode Yi and an address electrode Aj, and the adjacent common electrode Xi associated with the electrodes form a display cell Cij. The display cell Cij corresponds to a display pixel, thus making it possible to display a two-dimensional image in the display area 106.
FIG. 2A illustrates a display cell Cij of FIG. 1. The common electrodes Xi and the scan electrodes Yi are formed on a front glass substrate 211. On the top thereof, a dielectric layer 212 for insulating the electrodes from a discharge space 217 is deposited. Furthermore, on the top of the dielectric layer 212, an MgO (magnesium oxide) protective film 213 is deposited.
On the other hand, the address electrodes Aj are formed on a rear glass substrate 214 disposed so as to oppose to the front glass substrate 211. On the top of the address electrodes Aj, a dielectric layer 215 is deposited, on the top of which phosphor is deposited. Gas such as Ne+Xe Penning gas is sealed in the discharge space 217 between the MgO protective film 213 and the dielectric layer 215.
FIG. 2B is for explaining the capacitance Cp of an AC-driven plasma display. A capacitance Ca is the capacitance of the discharge space 217 between the common electrode Xi and the scan electrode Yi. A capacitance Cb is the capacitance of the dielectric layer 212 between the common electrode Xi and the scan electrode Yi. A capacitance Cc is the capacitance of the front glass substrate 211 between the common electrode Xi and the scan electrode Yi. The total of these capacitances Ca, Cb and Cc determines the capacitance between the electrodes Xi and Yi.
FIG. 2C is for explaining light emission of an AC driven plasma display. An array of red, blue, and green phosphors 218 is deposited on the inner surface of ribs 216 in the shape of a stripe for each color. A discharge between a common electrode Xi and a scan electrode Yi is adapted to excite the phosphor 218 to emit light 221.
FIG. 3 illustrates the structure of a frame FR of an image. For example, an image is formed at a rate of 60 frames per second. One frame FR consists of a first sub-frame SF1, a second sub-frame SF2, . . . , and an n-th sub-frame SFn, where n is equal to 10, for example, and corresponds to the number of gray scale bits. Hereinafter, one or each of the sub-frames SF1, SF2, . . . , SFn will be generally termed a sub-frame SF.
Each sub-frame SF consists of a reset period Tr, an address period Ta, and a sustain period Ts. During the address period Ta of each sub-frame SF, it is possible to select an “on” state or an “off” state of each display cell. The cell selected emits light during the sustain period Ts. Each sub-frame SF provides a different number of light emissions (time). This makes it possible to determine a gray scale level.
In the above construction, all the display lines corresponding to the scan electrodes Yi are sequentially scanned and addressed during the address period Ta; however, such a method can also be contemplated by which all the display lines are subdivided for scanning during the address period Ta. This method will be described below.
FIG. 4 illustrates a timing chart of a method for driving a plasma display by dividing the address period Ta into two. The address period Ta is divided into the first half address period Ta1 and the second half address period Ta2. The first half address period Ta1 is a period during which odd-numbered scan electrodes (odd-numbered lines) such as Y3 are scanned sequentially and addressed. The second half address period Ta2 is a period during which even-numbered scan electrodes (even-numbered lines) such as Y2 and Y4 are scanned sequentially and addressed.
First, during the reset period Tr, a predetermined voltage is applied between each scan electrode Yi and each common electrode Xi for full writing and full erasing with charges. In this way, the contents of the previous display are erased and predetermined wall charges are formed.
Next, during the first half address period Ta1, upon applying a pulse of positive potential Va to the address electrode Aj, the odd-numbered scan electrodes such as Y3 are scanned sequentially to apply thereto a negative potential pulse 403 of −Vs/2 (V). At this time, the potential of each electrode is shown in FIG. 5.
FIG. 5 illustrates the potential of each scan electrode when the scan electrode Y3 is scanned and addressed. The scan electrode Y2 is in a non-selected state at a positive potential 401 of +Vs/2 (V). The common electrode X3 is also at a positive potential 402 of +Vs/2 (V). The scan electrode Y3 is addressed to be in a selected state at a negative potential 403 of −Vs/2 (V). The common electrode X4 is at the ground potential 404. The scan electrode Y4 is in a non-selected state at a positive potential 405 of +Vs/2 (V). A positive potential Va is applied to the address electrode Aj.
In general, an address discharge 501 first occurs between the address electrode Aj and the scan electrode Y3. After this, by being triggered by the address discharge 501, a surface discharge 502 occurs between the scan electrode Y3 and the corresponding adjacent common electrode X3. This causes wall charges opposite in polarity to the applied voltage to be formed on each electrode. The wall charges cause a sustain discharge to occur between the common electrode X3 and the scan electrode Y3 during the subsequent sustain period Ts of FIG. 4, leading to a light emission.
Since the scan electrode Y2 is at the positive potential 401, the address discharge 501 causes a horizontal discharge 503 to occur. The discharge 503 extends horizontally to reach the scan electrode Y2. Consequently, the wall charges of the address electrode on the scan electrode Y2 are erased, thereby making it difficult to address the scan electrode Y2 during the subsequent second half address period Ta2. That is, wall charges cannot stably be formed on the even-numbered scan electrodes such as Y2 during the second half address period Ta2, thereby making it impossible to display stable images.
In this context, such a method may be contemplated by which the scan electrode Y2 is fixed to the ground potential during an address period Ta1. However, by the fixture, during the address period Ta1, the wall charges formed during the reset period Tr cannot be sustained, thereby raising a problem of making it impossible to address the scan electrode Y2. That is, a weak discharge is produced from the address electrode Aj to the scan electrode Y2, thereby causing the wall charges on the scan electrode Y2 to be cancelled. The weak discharge makes it difficult to address the scan electrode Y2 during the second half address period Ta2. The weak discharge depends in magnitude largely on temperature; the higher the temperature of the plasma display panel is, the larger the weak discharge is. This makes addressing more difficult.
Incidentally, during the second half address period Ta2 of FIG. 4, upon applying a pulse of positive potential Va to the address electrode Aj, pulses 411 and 415 of negative potential −Vs/2 (V) are applied by sequential scanning to the even-numbered scan electrodes such as Y2 and Y4. At this time, potentials 412, 413 and 414 are applied to the electrodes X3, Y3 and X4, respectively. This allows the even-numbered scan electrodes Y1 and Y4 to be addressed.
During the sustain period Ts, a voltage opposite in phase is applied between each common electrode Xi and each scan electrode Yi to establish a sustain discharge and emit light between the scan electrode Yi and the common electrode Xi corresponding to the display cell addressed during the address period Ta.